1. Field of the Invention
The invention relates to a memory unit with a bit line signal, and in particular relates to a memory unit receiving variable voltage supply to avoid data writing errors.
2. Description of the Related Art
FIG. 1 shows a conventional static random access memory (SRAM) 100 with five transistors 101, 102, 103, 104 and 105. A switch 101 is an NMOS transistor. The NMOS transistor 101 is turned on or turned off according to a word line signal WL to transmit a bit line signal BL to a memory unit 110. The memory 110 is formed by a latch circuit which comprises two inverters coupled cross over. The first inverter comprises an NMOS transistor 102 and a PMOS transistor 104. The second inverter comprises an NMOS transistor 103 and a PMOS transistor 105. Voltage levels of points B and C are opposite when storing digital data.
When the memory 100 is written by data 1, the voltage level of the bit line signal BL is pulled up to voltage Vdd and the word line signal WL turns on the NMOS transistor 101. Thus, the point B is at a high voltage level and the point C is at the low voltage level. When the memory 100 is written by data 0, the voltage level of the bit line signal BL is pulled down to voltage GND and the word line WL turns on the NMOS transistor 101. Thus, the point B is at a low voltage level and the point C is at a high voltage level.
When the memory storing data 1 is read, the bit line BL is precharged to voltage Vdd and then the word line WL turns on the NMOS transistor 101. Then, a memory system detects the voltage level of the bit line BL. Since the point B is at a high voltage level, the voltage level of the bit line BL will not be pulled down. Thus, the memory system detects the memory storing data 1.
When the memory storing data 0 is read, the bit line BL is precharged to voltage Vdd and then the word line WL turns on the NMOS transistor 101. Then, a memory system detects the voltage level of the bit line BL. Since the point C is at a high voltage level and the point B is at a low voltage level, the voltage level of the bit line BL will be pulled down. Thus, the memory system detects the memory storing data 0.
Because the memory comprises one bit line BL, when the memory is stored with data 1 (the point B is at high voltage level), the memory unit 110 can not be rewritten with data with a high voltage level. The conventional method is to adjust the beta ratio of transistors 102, 103, 104 and 105. However, the conventional method will cause instability with the memory unit 110. Thus, the objective of the invention is to solve the described problem.